Capacitor arrays are groups of parallel capacitors that form a single capacitance. Tunable capacitor arrays can comprise a base capacitor and binary weighted capacitors connected in parallel with the base capacitor. In typical applications, the Most Significant Bit (MSB) is a percentage of the base capacitor, and each lower bit is 50% of the previous bit. In many integrated circuit applications, the RC time constant of a circuit may need to be tuned to make corrections for process variation in typical value and temperature coefficients. Switchable binary capacitors can facilitate this tuning by allowing adjustments to the value of the circuit RC time constant. The capacitor values may be adjusted by enabling or disabling a switch in series with a portion of the total capacitance. Typically, the switches that are a part of such arrangements include MOSFET devices that are connected in series with the top plate of the capacitor. These switches can be turned on or off to add or remove parallel capacitance, and are controlled by digital registers in the logic control section of the circuit.
FIG. 1 is a diagram of a circuit having a typical integrator architecture. Capacitors Cbase and C0-Cn form a capacitor array, and switches M0 and Mn may be turned on or off to add or remove parallel capacitance to or from the array as described above. As is conventional, operational amplifier 101 receives an input signal through resistor R1 via input terminal Vi, and produces an output signal at output terminal Vo.
One analog method of testing the functionality of switches and control logic of binary tunable capacitors is to observe the step response of the circuit. According to this method, an integrator circuit, possessing a binary tunable capacitor (such as that shown in FIG. 1), is stimulated with a step input function. The step output response is then analyzed for information pertaining to aspects of the functionality of the tunable capacitors. As additional capacitance is added to the integrator, the rise time of the step response becomes slower. And, if the size of each capacitor added is sufficiently large, the change in rise time will be clearly evident and entirely measurable. However, if the size of the capacitor added is sufficiently small, the rise time change may be masked by other circuit phenomena and may not be measurable with sufficient resolution. Consequently, the rise time change may not be distinguishable so as to provide useful information. Another drawback of such methods, is that such tests only work for simple integrators. If the integrator configuration is complex, additional test circuitry is needed to configure it appropriately which is time consuming.
Another method entails measuring the bandwidth and center frequency of each device for every capacitor configuration code of the array. However, measuring the bandwidth and center frequency of each device, for every capacitor configuration code of the array, is time consuming. Moreover, circuit faults are not guaranteed to be found if they do not operate to dramatically alter circuit characteristics. As with other conventional testing methods, this method requires the use of complex and expensive analog testing equipment.